1. Field of the Invention
The present invention relates to a multilevel memory cell sense amplifier of a semiconductor device. Particularly, the present invention relates to a multilevel sensing circuit and a sensing method therefor, in which a secondary sensing input node is completely isolated, so that an effective deformation of the secondary sensing can be achieved, and its gain can be improved.
2. Description of the Prior Art
Generally, as the density of the DRAM is increased, its cells and the process become more fine. However, the chip size cannot be more reduced with the method of storing VCC or VSS into the cells, that is, with the presently exercised method.
However, if VCC, 2/3 VCC, 1/3 VCC and VCC can be stored and read, then the number of cells can be reduced to a half of that of the presently exercised method.
The multilevel sense amplifier will be specifically observed below referring to FIG. 1. As shown in this drawing, in the bit line and cells 2 and 4 of a DRAM, there are required: sense amplifiers 1 and 7 per bit line; a feedback element per bit line; a switching transistor 3 for dividing the bit line into two; and a comparator 5 consisting of an exclusive OR gate per bit line.
In the conventional sense amplifier, VCC ("1" data) or VSS ("0" data) is stored or read to and from a cell. However, in the multilevel sense amplifier, VCC ("1,1" data: strong one), 2/3VCC ("1,0" data: weak one), 1/3VCC ("0,1" data: weak zero), VSS ("0,0" data: strong zero) can be stored and read to and from a cell.
First, as shown in FIG. 2A, in the precharge period, an equalize signal EQU has a power source voltage VCC, and an NMOS transistors N7-N9 are all turned on. Therefore, bit lines BLL and BLR and bit line bars BLLB and BLRB are precharged with a half power source voltage (half VCC) (to be expressed "HVCC" below).
Under this condition, as shown in FIGS. 2C and 3D, VCT1 and VCT2 are all in a high voltage (VCC+=VPP), and therefore, sensing input nodes S3 and S4 of a second sense amplifier 7 is made to have a half power source voltage HVCC.
Here, an NMOS transistor N22 is precharged through an NMOS transistor N23, and therefore, the gate voltage of the NMOS transistor N23 has a half power source voltage HVCC, while the source has also a half power source voltage HVCC. Therefore, the node X4 of the comparator 5 has only a voltage HVCC-Vt, and thus, a problem occurs when carrying out the second data reading.
Second, in a read or write period, if a first word line WL1 is turned on to a high voltage VCC=VPP as shown in FIG. 2B, then an NMOS transistor N10 is turned on, with the result that the cell data is loaded on the bit lines BLL and BLR. Then the loaded data is transferred to the sensing input node S3 of the second sense amplifier 7. Then as shown in FIG. 2D, VCT2 is made to have a ground voltage VSS to turn off NMOS transistors N26 and N27. Thus the bit line BL and the sensing input node S3 of the second sense amplifier 7 are isolated from the bit line bar BLB and the sensing input node S4 of the second sense amplifier 7.
Then as shown in FIG. 2E, the first sense amplifier 1 which is connected through VSP1 and VSN1B to a sensing input node S1 and a sensing input node 52 is made active, thereby reading out a first data. As shown in FIG. 2F, a feedback voltage VFB is supplied with the power source voltage, and thus the coupling amount of capacitors C9 and C10 is adjusted through NMOS transistors V24 and N25 in accordance with the voltages of the right bit line BLR and the right bit line bar BLRB, i.e., the gate voltages of the NMOS transistors N24 and N15. Thus deformations are added to the sensing input node S3 and the sensing input node S4. Then VSP and VSN2B are operated as shown in FIG. 2G to activate the second sense amplifier 7, thereby reading out a second data.
Third, in a restore period, as shown in FIG. 2H, VMT0 is left in VCC+, while BMT1 is made to have a ground voltage VSS, thereby isolating the left bit line bar BLLB. Then the restore voltage VRST is supplied with VCC as shown in FIG. 2, and thus, in accordance with the potential of the node X4, if the node X4 is high, then the NMOS transistor N21 is turned on. Thus the node X1 is made to have VCC+, and through an NMOS transistor X2, there are shared the charge of left bit line BLL, the charge of the right bit line BLR, and the charge of the right bit line bar BLRB. Thus particular voltages (2/3VCC, 1/3VCC) are formed to be restored to the left and right memory cells 2 and 4.
In the above, the read and write of the multisensing operation were described.
In the conventional multisensing operation, if the node X4 is not precharged with HVCC, but is precharged with HVCC-Vtn, then a problem occurs. Now descriptions will be made on this matter.
In the case where the cell data are 1,0, that is, in the case where 2/3VCC is read out after its storing (the correct operation is carried out only if the data S1=VCC, S2=VSS, S3=VSS and S4=VCC are loaded), the equalize signal EQU is low so as to be disabled as shown in FIG. 4A. Therefore, a turning-off is done after precharging both the bit line BL and the bit line bar BLB.
Under this condition, the node X4 is considered to be precharged with HVCC, and the word line WL1 is turned on as shown in FIG. 4B, with the result that the data 2/3VCC of the left and right memory cells 2 and 4 are loaded on the bit line BL, and are also loaded on the sensing input node S3 of the second sense amplifier 7.
The data, which is loaded on the sensing input node S3 and on the bit line BL, is "HVCC+.DELTA.V", and VCT2 is low as shown in FIG. 4D. Therefore, the sensing input nodes S3 and S4 of the second sense amplifier 7 are isolated from the bit line BL and the bit line bar BLB, and then, the first sense amplifier 1 is activated by VSP1 and VSN1B as shown in FIG. 4E, thereby reading out a high data (S1=VCC and S2=VSS) as a first sensing.
Under this condition, As shown in FIG. 4L, a delta V10 justly shows a reduced sensing input margin compared with when VCC is stored in the left and right memory cells 2 and 4.
Under this condition, as shown in FIG. 4F, the feedback voltage VFB causes a variation in the second sensing input level. Under this condition, the VFB operating time greatly affects the variation of the sensing input node S4.
Here, the normal second sensing becomes possible only if a variation to S3="HVCC-.DELTA." is done owing to the feedback voltage VFB.
However, in this process, an actual problem occurs. That is, the right bit line BLR and the right bit line bar BLRB are spread from each other, with the result that the junction capacitors of the NMOS transistors N22 and N23 are coupled together. Consequently, an undesired deformation occurs in the sensing input nodes S3 and S4.
As shown in FIG. 4K, this deformation becomes severer, as the right bit line BLR and the right bit line bar BLRB are more spread from each other.
Therefore, when the right bit line BLR and the right bit line bar BLRB are not yet spread from each other, if the feedback voltage VFB is supplied, then the data deformation cannot be selectively carried out.
That is, the right bit line BLR should be high, with the result that the coupling of the capacitor C9 should occur very much through the NMOS transistor N24. Further, the right bit line bar BLRB should be low, with the result that the coupling of the capacitor C10 should occur to a small degree through the NMOS transistor N25. However, this phenomenon does not occur, and therefore, the sensing input nodes S3 and S4 cannot be deformed to the desired pattern (S3="HVCC-.DELTA.V", S4="GVCC+.DELTA.V).
For this reason, the optimization of the timing of the feedback voltage operation can be realized at a point where the undesired deformation due to the NMOS transistors N22 and N23 is small, and where selective operations of the NMOS transistors N24 and N25 are possible.
That is, it is at the point where the right bit line BLR is "HVCC+Vt", and the right bit line bar BLRB is "HVCC-Vt".
As shown in FIG. 8, in a simulation, it is at the point where if VCC=3.3 V, the right bit line BLR is 2.28 V, and the right bit liner bar BLRB is 0.89 V.
However, even if the operation of the feedback voltage VFB is optimized, normal operations for the respective data "1", "10", "01", "00" become difficult due to the undesired deformations by the node X4, which will be described below.
First, the node X4 will be described.
What potential (HVCC) the node X4 is precharged with gives a great influence to the second sensing input level.
That is, with the first sensing, if the right bit line BLR is spread to VCC, and if the right bit line bar BLRB is spread to VSS, then the right bit line BLR acts as the gate of the NMOS transistor N22 to turn on the NMOS transistor N22. Thus the node X4 and the node S4 are equalized, with the result that an undesired deformation occurs.
However, the node X4 can be actually precharged with only "HVCC-Vt", and therefore, a problem occurs.
That is, the first sensing causes that the right bit line BLR is spread to VCC, and the right bit line bar BLRB is spread to VSS until the right bit line BLR becomes "HVCC+Vt". Then the right bit line BLR acts as the gate voltage of the NMOS transistor N22 to turn on the NMOS transistor N22. Therefore, the node X4 and the sensing input node S4 begin to be equalized, with the ultimate result that the sensing input node S4 is greatly spread as shown in FIG. 13.
Under this greatly spread level, the sensing input node S4 should be laid upside down at a level higher than the node S3 through the NMOS transistor N24 owing to the feedback voltage VFB as shown in FIG. 4L. That is, S3="HVCC-.DELTA.V" and S4="HVCC+.DELTA.V" should be realized, but such an operation cannot occur, and therefore, the second sensing fails.
Even if the optimization in the operation of the feedback voltage VFB is realized, the problems of the node X4 is combined, with the result that the normal operations for the respective data "11", "10", "01" and "00" become difficult as shown in FIGS. 3 to 6.
Now the failures in the respective data will be described.
First, in the case where the data is "11", as shown in FIG. 7, the first data should be high (S3="HVCC+.DELTA.V" and S4="HVCC-.DELTA.V"), and the second data should also be high (S3="HVCC+.DELTA.V" and S4="HVCC-.DELTA.V").
Based on this pre-requisite, the situation will be considered. Upon carrying out the first sensing, the right bit line BLR and the right bit line bar BLRB begin to be spread toward VCC and VSS respectively, and the NMOS transistor N22 begins to be turned on. Further, the nodes X4 and S4 begin to be equalized, with the result that the potential of the sensing input node S4 is raised. Further, the potential of the node S4 is more raised due to the coupling between the capacitor C9 and the NMOS transistor N24 due to the feedback voltage VFB.
In the case of the data "11", the equalizing of the nodes X4 and S4 further aggravates the second sensing input margin.
Further, in the case of the data "11", due to the sustained coupling between the node S4 and the NMOS transistor N22, a data inversion occurs during the second sensing, thereby causing a failure.
Second, in the case of a data "10", as shown in FIG. 8, the first data should be high (S3="HVCC+.DELTA.V" and S4="HVCC-.DELTA.V"), and the second data should be low (S3="HVCC-.DELTA.V" and S4="HVCC+.DELTA.V").
To look into this matter, upon carrying out the first sensing, the right bit line BLR and the right bit line bar BLRB begin to be spread toward VCC and VSS respectively, and the NMOS transistor N22 is turned on. Further, the nodes X4 and S4 begin to be equalized, with the result that the potential of the sensing input node S4 is raised. Further, the potential of the node S4 is more raised due to the coupling between the capacitor C9 and the NMOS transistor N24 owing to the feedback voltage VFB.
In the case of the data "10", the equalizing of the nodes X4 and S4 improves the second sensing input margin.
Further, in the case of the data "10", due to the +sustained coupling between the node S4 and the NMOS transistor N22, the second sensing input margin is more improved, thereby excluding any problem.
Third, in the case where the data is "01", as shown in FIG. 9, the first data should be low (S3="HVCC-.DELTA.V" and S4="HVCC+.DELTA.V"), and the second data should be high (S3="HVCC+.DELTA.V" and S4="HVCC-.DELTA.V").
Based on this pre-requisite, the situation will be considered. Upon carrying out the first sensing, the right bit line BLR and the right bit line bar BLRB begin to be spread toward VCC and VSS respectively, and the NMOS transistor N23 begins to be turned on. Further, the nodes X4 and S4 begin to be equalized, with the result that the potential of the sensing input node S4 is raised. Further, the potential of the node S4 is more raised due to the coupling between the capacitor C10 and the NMOS transistor N25 owing to the feedback voltage VFB.
In the case of the data "01", the equalization of the nodes X4 and S4 improves the second sensing input margin.
Further, in the case of the data "01", due to the sustained coupling between the node S3 and the NMOS transistor N23, the second sensing input margin is more improved, thereby excluding any problem.
Fourth, in the case where the data is "00", as shown in FIG. 10, the first data should be low (s3="HVCC-.DELTA.V" and S4="HVCC+.DELTA.V"), and the second data should be also low (S3="HVCC-.DELTA.V" and S4="HVCC+.DELTA.V").
Based on this pre-requisite, the situation will be considered. Upon carrying out the first sensing, the right bit line BLR and the right bit line bar BLRB begin to be spread toward VCC and VSS respectively, and the NMOS transistor N23 begins to be turned on. Further, the nodes X4 and S4 begin to be equalized, with the result that the potential of the sensing input node S4 is raised. Further, the potential of the node S4 is more raised due to the coupling between the capacitor C10 and the NMOS transistor N25 owing to the feedback voltage VFB.
In the case of a data "00", the equalizing of the nodes X4 and S4 further aggravates the second sensing input margin.
Further, in the case of the data "00", due to the sustained coupling between the node S3 and the NMOS transistor N23, a data inversion occurs during the second sensing, thereby causing a problem.
In the above described operations for the respective data, the sustained couplings between the NMOS transistors N22 and N23 and the right bit line BLR, the right bit line bar BLRB and the sensing input nodes S3 and S4 give imbalances to the second sensing margin, thereby bringing failures.
Meanwhile, in the case of the restore, if the data is "10", then BLL=VCC, BLLB=VSS, BLR=VCC, BLRB=VSS, and node S4=VCC.
Under this condition, if VMT0=VCC+ and VMT1=VSS, and if the node X4 which has been in VCC is boosted to "VCC+.DELTA.V", then the node X1 should be in VCC+. Further, the left bit line BLL, the right bit line BLR and the right bit line bar BLRB should be charge-shared, and thus, a 2/3*VCC potential has to be restored.
In fact, however, the right bit line bar BLRB which has been in VSS is charge-shared so as to rise up to 2/3*VCC.
In this process, the NMOS transistor N23 which has been turned off is shifted to a turned-on status.
In this manner, the node X4 which has been in "VCC"+.DELTA.V is equalized to the sensing input node S3 which has been in VSS. Therefore, the sustained couplings between the NMOS transistors N22 and N23 and the right bit line BLR, the right bit line bar BLRB and the sensing input nodes S3 and S4 give imbalances to the second sensing margin, thereby bringing failures. Accordingly, there are produced the normal operations (the data "10" and "01") on the one hand, and failures (the data "11" and "00") on the other hand.
Further, when carrying out the restore, the node X4 becomes unstable.
That is, when carrying out the second sensing by the comparator 5 and the node X4, undesired interferences occur in the sensing input nodes S3 and S4.